1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method manufacturing method applied with strained-silicon technique.
2. Description of the Prior Art
With semiconductor processes entering the era of the deep submicron meter below 65 nanometer (nm), it has been more and more important to increase the metal-oxide semiconductor (MOS) drive current. To improve device performance, strained-silicon technique such as selective epitaxial growth (hereinafter abbreviated as SEG) method is developed to form epitaxial layers serving as the source/drain of the MOS. Because a lattice constant of the epitaxial layer is different from that of silicon, such characteristic is employed to cause alteration to the band structure of the silicon in the channel region. Accordingly, carrier mobility of the channel region is enhanced and thus device performance is improved.
Those skilled in the art have well known that the conventional MOS applied with SEG method is to form a disposal spacer on sidewalls of the gate structure or on a first spacer of the gate structure in order to define positions for forming recesses. Subsequently, recesses are formed and followed by performing a SEG method. Thus, epitaxial layers are formed in each recess. Thereafter the disposal spacer is removed and an ion implantation is subsequently performed to implant dopants of required conductivity type into the epitaxial layers. Accordingly, source/drain having the epitaxial layer are obtained. The epitaxial layers formed in the source/drain region render compressive or tensile stress to the channel region and thus the carrier mobility in the channel region is enhanced.
However, as size of the semiconductor structure keeps shrinking, semiconductor industries contrive to ensure that the device will not be impacted when forming or removing elements by which the device is constructed. For example, it has been found that the first spacer is always consumed and damaged when removing the disposal spacer. It even damages the profile of the gate structure when removing the disposal spacer. Furthermore, it is found that the size or profile of the second spacer and the source/drain are all adversely impacted when the first spacer is consumed. Seriously, it results that the following manufacturing processes fail to meet expectations.
Therefore, there is still a need for a manufacturing method for a semiconductor device that is able to protect elements of the semiconductor device from being impacted during removing the disposal spacer, and thus to ensure performance of the semiconductor device and the yield of the manufacturing method.